This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2008-0005074, filed on Jan. 16, 2008 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to buffer amplifiers and display drivers including buffer amplifiers, and more particularly to a buffer amplifier with reduced power range in an output stage for minimized power consumption in a display driver.
2. Background of the Invention
In general, a display device includes a display driver for driving a display panel, such as a liquid crystal display (LCD) panel. With diverse user demand for various-sized display devices, small sized display panels, medium sized display panels, large-sized display panels, and even super large sized display panels have been placed on the market.
FIG. 1 is a block diagram of a general display device including a display driver 110 and a display panel 120. Referring to FIG. 1, the display driver 110 includes a plurality of level shifters LS1, LS2, LS3, . . . , a plurality of digital to analog converters DAC1, DAC2, DAC3, . . . , and a plurality of buffer amplifiers BUF1, BUF2, BUF3, . . . . A respective level shifter, a respective digital to analog converter, and a respective buffer amplifier form each data path for generating a respective output signal from a respective input digital data signal for driving a respective data line of the display panel 120.
For example, the level shifter LS1, the digital to analog converter DAC1, and the buffer amplifier BUF1 form a path for driving a first data line (not shown) of the display panel 120 with the output signal Vout1 generated from the input digital data signal Data1. Similarly, the level shifter LS2, the digital to analog converter DAC2, and the buffer amplifier BUF2 form a path for driving a second data line (not shown) of the display panel 120 with the output signal Vout2 generated from the input digital data signal Data2. Also, the level shifter LS3, the digital to analog converter DAC3, and the buffer amplifier BUF3 form a path for driving a third data line (not shown) of the display panel 120 with the output signal Vout3 generated from the input digital data signal Data3.
Each of the level shifters LS1, LS2, and LS3 shifts a respective voltage level of a respective one of the input digital data signals Data1, Data2, and Data3. Each of the digital to analog converters DAC1, DAC2, and DAC3 converts a respective shifted digital data signal into a respective one of analog data signals Vin1, Vin2, and Vin3. Each of the buffer amplifiers BUF1, BUF2, and BUF3 receives a respective one of the analog data signals Vin1, Vin2, and Vin3 from the digital to analog converters DAC1, DAC2, and DAC3. Also, each of the buffer amplifiers BUF1, BUF2, and BUF3 generates a respective one of the output signals Vout1, Vout2, and Vout3 corresponding to a respective one of the input signals Vin1, Vin2, and Vin3.
A high power voltage VDD and a low power voltage VSS are applied to each of the buffer amplifiers BUF1, BUF2, and BUF3 that directly drive the display panel 120. The larger the size of the display panel 120, the greater the driving burden of the buffer amplifiers BUF1, BUF2, and BUF3, and the more power consumed by the buffer amplifiers BUF1, BUF2, and BUF3. An increase in power consumption which causes an increase in a calorific value is a significant design constraint of a display driver.